1. Field
Example embodiments relate to a nonvolatile memory transistor, a nonvolatile memory device having the same and methods of fabricating the same. Other example embodiments relate to a nonvolatile memory transistor having a poly-silicon fin, a stacked nonvolatile memory device having the transistor and methods of fabricating the same.
2. Description of the Related Art
In a semiconductor device employing a planar type transistor including a gate electrode formed on a semiconductor substrate and junction regions formed at both sides of the gate electrode, as the integration degree of the semiconductor device increases, attempts have been made to reduce the length of a channel. However, when reducing the length of the channel, short channel effects, e.g., drain induced barrier lowering (DIBL), a hot carrier effect and punch through, may occur. In order to prevent or reduce such short channel effects, various methods have been introduced including a method of reducing the depth of the junction region, and a method of extending the relative length of the channel by forming a groove in the channel. However, as the length of the channel is reduced down to about 50 nm or so, the methods of preventing or reducing such short channel effects have also reached limits.